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MB39C605 데이터시트(PDF) 12 Page - Cypress Semiconductor |
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MB39C605 데이터시트(HTML) 12 Page - Cypress Semiconductor |
12 / 26 page Document Number: 002-08444 Rev. *B Page 12 of 26 MB39C605 8.3 Power-On Sequence When the AC line voltage is supplied, VBULK is powered from the AC line through a diode bridge and a diode (D1) with charging a capacitor (CBULK), and the VDD pin is charged from VBULK through a start-up resistance (Rst). (Figure 8-3 red path) When the VDD pin is charged up and the voltage on the VDD pin (VVDD) rises above the UVLO threshold voltage, an internal Bias circuit starts operating, and MB39C605 starts the dimming control. After the UVLO is released, this device enables switching and is operating in a forced switching mode (TON = 1.5 µs, TOFF = 78 µs to 320 µs). When the voltage on the TZE pin reaches the Zero energy threshold voltage (VTZETH = 0.7V), MB39C605 enters normal operation mode. After the switching begins, the VDD pin is also charged from Auxiliary Winding through an external diode (DBIAS). (Figure 8-3 blue path) During start-up period VVDD is not supplied from Auxiliary Winding, because the LED voltage is low. VVDD decreases gradually until the LED voltage rises above enough high that the Auxiliary Winding voltage can exceed VVDD. In this period, if VVDD falls below the UVLO threshold voltage, the switching stops. When the VDD pin is charged up again and VVDD rises above the UVLO threshold voltage, MB39C605 restarts the switching. This device repeats above operation until the LED voltage rises above enough high. VVDD becomes stable after that. Figure 8-3. VDD Supply Path at Power-On Figure 8-4. Power-On Waveform UVLO VDD DRV CS GND Internal Bias Generator Driver VBULK0 PWM Control Logic To TZE DBIAS 8 6 7 1 VBULK Phase Dimmer Rst D1 CBULK VBULK0 DRV VDD VLED TZE VTZETH = 0.7V Force switching (TON=1.5µs/TOFF=78µs to 320µs) Switching start UVLO Vth = 13V Normal switching VBULK |
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