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SN74AUP1T97 데이터시트(PDF) 2 Page - Texas Instruments |
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SN74AUP1T97 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 15 page SN74AUP1T97 SINGLESUPPLY VOLTAGE LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS SCES613A – OCTOBER 2004 − REVISED DECEMBER 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUP1T97YEPR _ _ _TH_ −40 °C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUP1T97YZPR _ _ _TH_ SOT (SOT-23) − DBV Tape and reel SN74AUP1T97DBVR HT4_ SOT (SC-70) − DCK Tape and reel SN74AUP1T97DCKR TH_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-to-1 data selector 5 2-input AND gate 6 2-input OR gate with one inverted input 7 2-input NAND gate with one inverted input 7 2-input AND gate with one inverted input 8 2-input NOR gate with one inverted input 8 2-input OR gate 9 Inverter 10 Noninverted buffer 11 |
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