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TC55V8512FTI-12 데이터시트(HTML) 3 Page - Toshiba Semiconductor

부품명 TC55V8512FTI-12
상세내용  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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제조사  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TC55V8512FTI-12 데이터시트(HTML) 3 Page - Toshiba Semiconductor

 
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TC55V8512JI/FTI-12,-15
2001-12-19
3/10
DC CHARACTERISTICS (Ta
==== −−−−40° to 85°C, VDD ==== 3.3 V ±±±± 0.3 V)
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
IIL
Input Leakage Current
(Except NU pin)
VIN = 0 to VDD
−1
1
µA
ILO
Output Leakage
Current
CE
= VIH or WE = VIL or OE = VIH,
VOUT = 0 to VDD
−1
1
µA
VIN = 0 to 0.8 V
−1
20
II (NU)
Input Current
(NU pin)
VIN = 0 to 0.2 V
−1
1
µA
IOH = −2 mA
2.4
VOH
Output High Voltage
IOH = −100 µA
VDD − 0.2
IOL = 2 mA
0.4
VOL
Output Low Voltage
IOL = 100 µA
0.2
V
tcycle = 12 ns
180
tcycle = 15 ns
150
tcycle = 20 ns
140
IDDO
Operating Current
CE
= VIL, IOUT = 0 mA,
OE
= VIH,
Other Input
= VIH/VIL
tcycle = 25 ns
120
mA
IDDS1
CE
= VIH, Other Input = VIH or VIL
55
IDDS2
Standby Current
CE
= VDD − 0.2 V, Other Input = VDD − 0.2 V or 0.2 V
10
mA
CAPACITANCE (Ta
==== 25°C, f ==== 1 .0 MHz)
SYMBOL
PARAMETER
TEST CONDITION
MAX
UNIT
CIN
Input Capacitance
VIN = GND
6
pF
CI/O
Input/Output Capacitance
VI/O = GND
8
pF
Note:
This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE
CE
OE
WE
I/O1 to I/O8
POWER
Read
L
L
H
Output
IDDO
Write
L
*
L
Input
IDDO
Outputs Disable
L
H
H
High Impedance
IDDO
Standby
H
*
*
High Impedance
IDDS
* : Don’t care
Note:
The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8 V to the NU.


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