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CY7C1460KV25 데이터시트(PDF) 1 Page - Cypress Semiconductor

부품명 CY7C1460KV25
상세설명  36-Mbit (1M36/2M18) Pipelined SRAM with NoBL??Architecture (With ECC)
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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36-Mbit (1M × 36/2M × 18)
Pipelined SRAM
with NoBL™ Architecture (With ECC)
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-66679 Rev. *J
Revised February 7, 2018
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250 MHz bus operations with zero wait states
Available speed grades are 250 MHz, 200 MHz, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
2.5 V core power supply
2.5 V I/O power supply
Fast clock-to-output times
2.5 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and
CY7C1462KVE25 available in JEDEC-standard Pb-free
100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA
packages.
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability — linear or interleaved burst order
“ZZ” sleep mode option
On-chip error correction code (ECC) to reduce soft error rate
(SER)
Functional Description
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous
pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic,
respectively. They are designed to support unlimited true
back-to-back read/write operations with no wait states. The
CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are equipped with the advanced NoBL logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data in systems that require frequent
write/read transitions. The CY7C1460KV25/CY7C1462KV25/
CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
BWa–BWd
for
CY7C1460KV25/CY7C1460KVE25
and
BWa–BWb for CY7C1462KV25/CY7C1462KVE25 and a write
enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum access time
2.5
3.2
3.4
ns
Maximum operating current
× 18
220
190
170
mA
× 36
240
210
190


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