CY7C1460KV33 datasheet(13/31 Pages) CYPRESS

부품명	CY7C1460KV33

상세설명	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)

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13 / 31 page

Document Number: 001-66680 Rev. *L

Page 13 of 31

CY7C1460KV33

CY7C1460KVE33

CY7C1462KVE33

IEEE 1149.1 Serial Boundary Scan (JTAG)

CY7C1460KVE33 incorporates a serial boundary scan test

access port (TAP). This part is fully compliant with 1149.1. The

TAP operates using JEDEC-standard 3.3-V or 2.5-V I/O logic

level.

The CY7C1460KVE33 contains a TAP controller, instruction

register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are pulled

up internally and may be unconnected. They may alternately be

connected to VDD through a pull-up resistor. TDO should be left

unconnected. Upon power-up, the device enters a reset state,

which does not interfere with the operation of the device.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this ball unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

register between TDI and TDO is chosen by the instruction that

is loaded into the TAP instruction register. TDI is pulled up

internally and can be unconnected if the TAP is unused in an

application. TDI is connected to the most significant bit (MSB) of

any register (see TAP Controller Block Diagram).

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine. The output changes on the falling edge

of TCK. TDO is connected to the least significant bit (LSB) of any

register (see TAP Controller State Diagram).

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO

comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test circuitry.

Only one register can be selected at a time through the

instruction register. Data is serially loaded into the TDI ball on the

rising edge of TCK. Data is output on the TDO ball on the falling

edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO balls as shown in the TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary “01” pattern to enable

fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between the

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW (VSS)

when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM. The length of the boundary scan

register for the SRAM in different packages is listed in the Scan

Register Sizes table.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR state

and is then placed between the TDI and TDO balls when the

controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used to

capture the contents of the I/O ring.

The Boundary Scan Order on page 19 and show the order in

which the bits are connected. Each bit corresponds to one of the

bumps on the SRAM package. The MSB of the register is

connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in the Identification Register Definitions on

page 18.

유사한 부품 번호 - CY7C1460KV33

제조업체	부품명	데이터시트	상세설명
Cypress Semiconductor	CY7C1460KV25	830Kb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV25-167AXC	830Kb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV25-167BZC	830Kb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV25-167BZXI	830Kb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV25-200BZI	830Kb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)

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유사한 설명 - CY7C1460KV33

제조업체	부품명	데이터시트	상세설명
Cypress Semiconductor	CY7C1460KV25	830Kb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460SV25	429Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370KV33	999Kb / 32P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1440KV33	3Mb / 33P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)
	CY7C1461KV33	2Mb / 23P	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1370KV25	2Mb / 30P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370B	759Kb / 27P	512K 횞 36/1M 횞 18 Pipelined SRAM with NoBL Architecture
	CY7C1371KV33	682Kb / 24P	18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM with NoBL??Architecture (With ECC)
	CY7C1441KV33	1Mb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM (With ECC)
	CY7C1460BV25	721Kb / 30P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture

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