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CY7C1481BV25 데이터시트(PDF) 15 Page - Cypress Semiconductor

부품명 CY7C1481BV25
상세설명  72-Mbit (2 M 횞 36) Flow-Through SRAM
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1481BV25 데이터시트(HTML) 15 Page - Cypress Semiconductor

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CY7C1481BV25
Document Number: 001-74847 Rev. *B
Page 15 of 21
Figure 5. Read/Write Cycle Timing [21, 22, 23]
Timing Diagrams (continued)
tCYC
t
CL
CLK
tADH
tADS
ADDRESS
t
CH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3
A4
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
t
WEH
t
WES
t
OEHZ
tDH
tDS
tCDV
tOELZ
A1
A5
A6
D(A5)
D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
ADSP
ADSC
BWE, BW X
CE
ADV
OE
Data In (D)
Data Out (Q)
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
22. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.


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