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2 / 29 page Document Number: 001-44061 Rev. *L Page 2 of 29 CY7C1648KV18 CY7C1650KV18 Logic Block Diagram – CY7C1648KV18 Logic Block Diagram – CY7C1650KV18 Write Reg Write Reg CLK A(21:0) Gen. K K Control Logic Address Register Read Data Reg. R/W Output Logic Reg. Reg. Reg. 18 36 18 BWS[1:0] VREF 18 22 18 LD Control R/W DOFF 18 DQ[17:0] 18 CQ CQ QVLD Write Reg Write Reg CLK A(20:0) Gen. K K Control Logic Address Register Read Data Reg. R/W Output Logic Reg. Reg. Reg. 36 72 36 BWS[3:0] VREF 36 21 36 LD Control R/W DOFF 36 DQ[35:0] 36 CQ CQ QVLD |
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