TC90A58F

2002-02-06

11

12. Built-in HPLL

registers.

· Divider control (when using internal divider): DIVIIC3~DIVIIC0 in Sub-Address 14H

CKSEL[3:0] is enabled only when DIVIIC3~DIVIIC0 in is all 0s.

· Selection of phase comparator (PC) in HPLL (PC2 or PC3): PCSEL0~PCSEL1 in Sub-Address 01H

· Selection of divider (internal or external): DIVSEL in Sub-Address 01H

· HPLL oscillation/oscillation halt: HPLLSTOP in Sub-Address 01H

13. 10-Bit ADC

The TC90A58F can also be used as a 10-bit AD converter. This setting can be made using the M10B bit in

Note that when the device is used as a 10-bit AD converter, only two channels (the Y and Cb signals) are

output from the following output pins.

Y signal: ROUT[7:0], GOUT[7:6]

Cb signal: GOUT[1:0], BOUT[7:0]

When the TC90A58F is used as a 10-bit AD converter, only certain functions can be used.

【

Available functions】

1.

Low-pass filter

2.

Output format setting (4:4:4 only)

3.

Y delay (Y signal only)

4.

Color bar generation (4:4:4 only)

5.

HDOUT timing adjustment

6.

VDOUT timing adjustment

8.

9.

Countermeasure against HDIN and VDIN pulse noise

10. Countermeasure against VDIN noise

11. Clamp pulse timing

12. HPLL settings

14. Clamp level setting

【

Unavailable functions】

Processing for R601, R656, 4:1:1 and 4:2:2 modes (for functions 2, 4 and 7 in the list of available

functions shown above)

V mask

HREF

HD

VD

Dedicated

Dedicated

AVDD

AVSS

Gyrator type

DIVSEL

(ECL

PC3

PC2

PCSEL

IFIL

BFIL

AGCOFF

DIVN

HDIV

VCO1

OUTSEL

Full-scale square wave

APCLK

BUFFER

TEST

2

(div: 1896/948/880/660)

(29.82 MHz/29.82 MHz/

29.7 MHz/29.7 MHz)

(15.75/31.5/

33/45 kHz)

AGC

Figure 5

Block Diagram of HPLL