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S71PL254 데이터시트(HTML) 5 Page - SPANSION

부품명 S71PL254
상세내용  STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
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S71PL254 데이터시트(HTML) 5 Page - SPANSION

 
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November 22, 2004 S71PL254/127/064/032J_00_A6
5
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I n f o rmatio n
Figure 6. Data# Polling Algorithm......................................... 76
RY/BY#: Ready/Busy# .......................................................................................76
DQ6: Toggle Bit I ................................................................................................76
Figure 7. Toggle Bit Algorithm.............................................. 78
DQ2: Toggle Bit II .............................................................................................. 78
Reading Toggle Bits DQ6/DQ2 ..................................................................... 78
DQ5: Exceeded Timing Limits ........................................................................79
DQ3: Sector Erase Timer .................................................................................79
Table 19. Write Operation Status ......................................... 80
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 81
Figure 8. Maximum Overshoot Waveforms............................. 81
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .82
Industrial (I) Devices ......................................................................................... 82
Wireless Devices ............................................................................................... 82
Supply Voltages ................................................................................................... 82
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 20. CMOS Compatible ................................................ 83
AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .84
Test Conditions .................................................................................................. 84
Figure 9. Test Setups......................................................... 84
Table 21. Test Specifications ............................................... 84
Switching Waveforms ....................................................................................... 85
Table 22. Key to Switching Waveforms ................................. 85
Figure 10. Input Waveforms and Measurement Levels............. 85
VCC RampRate .................................................................................................. 85
Read Operations ................................................................................................ 86
Table 23. Read-Only Operations .......................................... 86
Figure 11. Read Operation Timings....................................... 86
Figure 12. Page Read Operation Timings ............................... 87
Reset ...................................................................................................................... 87
Table 24. Hardware Reset (RESET#) .................................... 87
Figure 13. Reset Timings..................................................... 88
Erase/Program Operations ............................................................................. 89
Table 25. Erase and Program Operations .............................. 89
Timing Diagrams ................................................................................................. 90
Figure 14. Program Operation Timings .................................. 90
Figure 15. Accelerated Program Timing Diagram .................... 90
Figure 16. Chip/Sector Erase Operation Timings..................... 91
Figure 17. Back-to-back Read/Write Cycle Timings ................. 91
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 92
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 92
Figure 20. DQ2 vs. DQ6 ...................................................... 93
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 26. Temporary Sector Unprotect ................................. 93
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 93
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 94
Controlled Erase Operations ..........................................................................95
Table 27. Alternate CE# Controlled Erase and
Program Operations ........................................................... 95
Table 28. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 96
Table 29. Erase And Programming Performance .................... 97
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 97
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Product Information . . . . . . . . . . . . . . . . . . . . . . . 98
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 99
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 99
Power Up ..............................................................................................................99
Figure 23. Power Up 1 (CS1# Controlled) ............................. 99
Figure 24. Power Up 2 (CS2 Controlled)................................ 99
Functional Description . . . . . . . . . . . . . . . . . . . . . 100
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 100
DC Recommended Operating Conditions . . . . . 100
DC and Operating Characteristics . . . . . . . . . . . 101
Common ...............................................................................................................101
16M pSRAM ..........................................................................................................102
32M pSRAM .........................................................................................................102
64M pSRAM .........................................................................................................103
AC Operating Conditions . . . . . . . . . . . . . . . . . . 103
Test Conditions (Test Load and Test Input/Output Reference) ........103
Figure 25. Output Load .................................................... 103
ACC Characteristics (Ta = -40°C to 85°C, VCC = 2.7 to 3.1 V) ........104
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 105
Read Timings .......................................................................................................105
Figure 26. Timing Waveform of Read Cycle(1)..................... 105
Figure 27. Timing Waveform of Read Cycle(2)..................... 105
Figure 28. Timing Waveform of Read Cycle(2)..................... 105
Write Timings .....................................................................................................106
Figure 29. Write Cycle #1 (WE# Controlled)........................ 106
Figure 30. Write Cycle #2 (CS1# Controlled) ...................... 106
Figure 31. Timing Waveform of Write Cycle(3)
(CS2 Controlled) ............................................................. 107
Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ..................................................................... 107
pSRAM Type 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 30. DC Recommended Operating Conditions ............... 109
Table 31. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to
3.3V) ............................................................................. 110
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 32. AC Characteristics and Operating Conditions (TA = -25°C
to 85°C, VDD = 2.6 to 3.3V) .............................................. 110
Table 33. AC Test Conditions ............................................. 111
Figure 33. AC Test Loads .................................................. 111
Figure 34. State Diagram ................................................. 112
Table 34. Standby Mode Characteristics .............................. 112
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 35. Read Cycle 1—Addressed Controlled ................... 112
Figure 36. Read Cycle 2—CS1# Controlled.......................... 113
Figure 37. Write Cycle 1—WE# Controlled .......................... 113
Figure 38. Write Cycle 2—CS1# Controlled ......................... 114
Figure 39. Write Cycle3—UB#, LB# Controlled .................... 114
Figure 40. Deep Power-down Mode .................................... 115
Figure 41. Power-up Mode ................................................ 115
Figure 42. Abnormal Timing.............................................. 115
pSRAM Type 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Functional Description . . . . . . . . . . . . . . . . . . . . . 116
Product Portfolio ................................................................................................116
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 117


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