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TC58DVM92A1FTI0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TC58DVM92A1FTI0
์ƒ์„ธ๋‚ด์šฉ  TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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TC58DVM92A1FTI0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Toshiba Semiconductor

 
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TC58DVM92A1FTI0
2003-07-11
4/44
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
- 40ยฐ to 85ยฐC, VCC
2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
tCLS
CLE Setup Time
0
ns
tCLH
CLE Hold Time
10
ns
tCS
CE
Setup Time
0
ns
tCH
CE
Hold Time
10
ns
tWP
Write Pulse Width
25
ns
tALS
ALE Setup Time
0
ns
tALH
ALE Hold Time
10
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
10
ns
tWC
Write Cycle Time
50
ns
tWH
WE
High Hold Time
15
ns
tWW
WP
High to WE
Low
100
ns
tRR
Ready to RE Falling Edge
20
ns
tRP
Read Pulse Width
35
ns
tRC
Read Cycle Time
50
ns
tREA
RE
Access Time (Serial Data Access)
35
ns
tCEA
CE
Access Time (Serial Data Access, ID Read)
45
ns
tALEA
ALE Access Time (ID Read)
45
ns
tCEH
CE
High Time for Last Address in Serial Read Cycle
100
ns
(2)
tREAID
RE
Access Time (ID Read)
35
ns
tOH
Data Output Hold Time
10
ns
tRHZ
RE
High to Output High Impedance
30
ns
tCHZ
CE
High to Output High Impedance
20
ns
tREH
RE
High Hold Time
15
ns
tIR
Output-High-impedance-to- RE Falling Edge
0
ns
tRSTO
RE
Access Time (Status Read)
35
ns
tCSTO
CE
Access Time (Status Read)
45
ns
tRHW
RE
High to WE
Low
0
ns
tWHC
WE
High to CE Low
30
ns
tWHR
WE
High to RE Low
30
ns
tR
Memory Cell Array to Starting Address
25
s
tWB
WE
High to Busy
200
ns
tAR2
ALE Low to RE Low (Read Cycle)
50
ns
tRB
RE
Last Clock Rising Edge to Busy (in Sequential Read)
200
ns
tCRY
CE
High to Ready (When interrupted by CE in Read Mode)
1
tr (
BY
/
RY
)
s
(1) (2)
tRST
Device Reset Time (Read/Program/Erase)
6/10/500
s
AC TEST CONDITIONS
PARAMETER
CONDITION
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3 ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
Output load
CL (100 pF)
1 TTL


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