전자부품 데이터시트 검색엔진 |
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GS1522 데이터시트(PDF) 5 Page - Gennum Corporation |
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GS1522 데이터시트(HTML) 5 Page - Gennum Corporation |
5 / 20 page GENNUM CORPORATION 522 - 26 - 00 5 PIN DESCRIPTIONS NUMBER SYMBOL LEVEL TYPE DESCRIPTION 1, 95 VEE3 Power Input Negative Supply. Most negative power supply connection, for input stage. 2 PCLK_IN TTL Input Parallel Data Clock. 74.25 or 74.25/1.001MHz 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 19, 20, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,46, 50, 51, 52, 56, 60, 61, 62, 65, 66, 67, 68, 69, 70, 71, 72, 73, 80, 81, 83, 93, 97, 98, 99, 100, 101, 102, 108, 109, 116, 117, 120, 121 NC No Connect. These pins are not used internally. These pins should be floating. 10 BUF_VEE Power TEST Negative Supply/Test Pin. Most negative power supply connection. For buffer for oscillator/divider for test purposes only. Leave floating for normal operation. 13 XDIV20 TTL TEST Test Pin. Test block output. Leave floating for normal operation. 15 PLL_LOCK TTL Output Status Signal Output. Indicates when the GS1522 is phase locked to the incoming PCLK_IN clock signal. LOGIC HIGH indicates PLL is in Lock. LOGIC LOW indicates PLL is out of Lock. 16 BYPASS TTL Input Control Signal Input. Used to bypass the scrambling function if data is already scrambled by GS1501 or if non-SMPTE encoded data stream such as 8b/10b is to be transmitted. When BYPASS is LOW, the SMPTE scrambler and NRZ(I) encoder are enabled. When BYPASS is HIGH, the SMPTE scrambler and NRZ(I) encoder are bypassed. 17 RESET TTL Input Control Signal Input. Used to reset the SMPTE scrambler. For logic HIGH; Resets the SMPTE scrambler and NRZ(I) encoder. For logic LOW: normal SMPTE scrambler and NRZ(I) encoder operation. 18, 26, 27, 28, 29, 30, 59 VEE2 Power Input Negative Supply. Most negative power supply connection. For Cable Driver outputs and all other digital circuitry excluding input stage and PLL stage. 21, 22, 23, 24, 25, 45, 57 VCC2 Power Input Positive Supply. Most positive power supply connection. For Cable Driver outputs and all other digital circuitry excluding input stage and PLL stage. 31 SDO1_EN Power Input Control Signal Input. Used to enable or disable the second serial data output stage. This signal must be tied to GND to enable this stage. Do not connect to a logic low. 44 RSET1 Input Control Signal Input. External resistor is used to set the data output amplitude for SDO1 and SDO1. Use a ±1% resistor. 47, 49 SDO1+, SDO1- Analog Output Serial Data Output Signal. Current mode serial data output #1. Use 75 Ω ±1% pull up resistors to V CC2 . 48, 54 SDO_NC No Connect. Not used internally. This pin must be left floating. 53, 55 SDO0+, SDO0- Analog Output Serial Data Output Signal. Current mode serial data output #0. Use 75 Ω ± 1% pull up resistors to V CC2 . |
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