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SN74GTLP2033DGVR 데이터시트(PDF) 5 Page - Texas Instruments |
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SN74GTLP2033DGVR 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 15 page SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables (Continued) LOOPBACK LOOPBACK Q† L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram). SELECT INPUTS SELECTED LOGIC MODE1 MODE0 ELEMENT L L Buffer L H Flip-flop H X Latch FLIP-FLOP INPUTS OUTPUT CLK/ LE DATA OUTPUT L X Q0 ↑ LH ↑ H L B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC OUTPUT B-PORT LOGIC LEVEL EDGE RATE H Slow L Fast |
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