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AM41DL3208G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 41 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM41DL3208G
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM41DL3208G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 41 Page - SPANSION

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Am41DL3208G
February 13, 2002
P R E L IMINARY
Notes:
1. The I
CC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum I
CC specifications are tested with VCC = VCCmax.
3. I
CC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Leakage Current
V
IN = VSS to VCC
โ€“1.0
1.0
ยตA
I
LO
Output Leakage Current
CE1#s = V
IH, CE2s = VIL or OE# =
V
IH or WE# = VIL, VIO= VSS to VCC
โ€“1.0
1.0
ยตA
ICC
Operating Power Supply Current
I
IO = 0 mA, CE1#s = VIL, CE2s =
WE# = VIH, VIN = VIH or VIL
3mA
I
CC1s
Average Operating Current
Cycle time = 1 ยตs, 100% duty,
I
IO = 0 mA, CE1#s โ‰ค 0.2 V,
CE2
โ‰ฅ V
CC โ€“ 0.2 V, VIN โ‰ค 0.2 V or
V
IN โ‰ฅ VCC โ€“ 0.2 V
3mA
I
CC2s
Average Operating Current
Cycle time = Min., I
IO = 0 mA,
100% duty, CE1#s = V
IL, CE2s =
VIH, VIN = VIL = or VIH
30
mA
V
OL
Output Low Voltage
I
OL = 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH = โ€“1.0 mA
2.4
V
I
SB
Standby Current (TTL)
CE1#s = V
IH, CE2 = VIL, Other
inputs = V
IH or VIL
0.3
mA
I
SB1
Standby Current (CMOS)
CE1#s
โ‰ฅ V
CC โ€“ 0.2 V, CE2 โ‰ฅ VCC โ€“
0.2 V (CE1#s controlled) or CE2
โ‰ค
0.2 V (CE2s controlled), CIOs =
V
SS or VCC, Other input = 0 ~ VCC
15
ยตA


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