 |
์ ์๋ถํ ๋ฐ์ดํฐ์ํธ ๊ฒ์์์ง |
|
|
์ ์๋ถํ ๋ฐ์ดํฐ์ํธ ๊ฒ์์์ง |
|
AM41DL3208G ๋ฐ์ดํฐ์ํธ(HTML) 41 Page - SPANSION |
|
||||||||||||||||||||||||||||||
AM41DL3208G ๋ฐ์ดํฐ์ํธ(HTML) 41 Page - SPANSION |
|
|
41 / 65 page 
40 Am41DL3208G February 13, 2002 P R E L IMINARY Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit I LI Input Leakage Current V IN = VSS to VCC โ1.0 1.0 ยตA I LO Output Leakage Current CE1#s = V IH, CE2s = VIL or OE# = V IH or WE# = VIL, VIO= VSS to VCC โ1.0 1.0 ยตA ICC Operating Power Supply Current I IO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL 3mA I CC1s Average Operating Current Cycle time = 1 ยตs, 100% duty, I IO = 0 mA, CE1#s โค 0.2 V, CE2 โฅ V CC โ 0.2 V, VIN โค 0.2 V or V IN โฅ VCC โ 0.2 V 3mA I CC2s Average Operating Current Cycle time = Min., I IO = 0 mA, 100% duty, CE1#s = V IL, CE2s = VIH, VIN = VIL = or VIH 30 mA V OL Output Low Voltage I OL = 2.1 mA 0.4 V V OH Output High Voltage I OH = โ1.0 mA 2.4 V I SB Standby Current (TTL) CE1#s = V IH, CE2 = VIL, Other inputs = V IH or VIL 0.3 mA I SB1 Standby Current (CMOS) CE1#s โฅ V CC โ 0.2 V, CE2 โฅ VCC โ 0.2 V (CE1#s controlled) or CE2 โค 0.2 V (CE2s controlled), CIOs = V SS or VCC, Other input = 0 ~ VCC 15 ยตA |
Korean โผ 
English
Chinese
German
Japanese
Russian
Spanish
French
Italian
Portuguese
Polish
Vietnamese
