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AM41DL3208G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 49 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM41DL3208G
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM41DL3208G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 49 Page - SPANSION

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Am41DL3208G
February 13, 2002
P R E L IMINARY
AC CHARACTERISTICS
Figure 19.
Accelerated Program Timing Diagram
OE#
WE#
CE#f
VCCf
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC
tAS
tWPH
tVCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
tGHWL
tCS
Status
DOUT
Program Command Sequence (last two cycles)
RY/BY#
tRB
tBUSY
tCH
PA
Notes:
1. PA = program address, PD = program data, D
OUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 18.
Program Operation Timings
WP#/ACC
tVHH
VHH
VIL or VIH
VIL or VIH
tVHH


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