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AM41DL3208G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 59 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM41DL3208G
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM41DL3208G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 59 Page - SPANSION

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Am41DL3208G
February 13, 2002
P R E L IMINARY
AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
CW is measured from CE1#s going low to the end of write.
3. t
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP is measured from the beginning of write
to the end of write.
Figure 30.
SRAM Write Cycleโ€”WE# Control
Parameter
Symbol
Description
Speed Options
Unit
70
85
tWC
Write Cycle Time
Min
70
85
ns
t
Cw
Chip Enable to End of Write
Min
60
70
ns
tAS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
60
70
ns
tBW
UB#s, LB#s to End of Write
Min
60
70
ns
t
WP
Write Pulse Time
Min
50
60
ns
tWR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
0
ns
Max
20
25
t
DW
Data to Write Time Overlap
Min
30
35
ns
tDH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
min
5
ns
Address
CS1#s
Data Undefined
UB#s, LB#s
WE#
Data In
Data Out
tWC
tCW
(See Note 2)
tAW
High-Z
High-Z
Data Valid
CS2s
tCW
(See Note 2)
tBW
tWP
(See Note 5)
tAS
(See Note 4)
tWR (See Note 3)
tBW
tDW
tDH
tOW


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