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AM41DL3208G 데이터시트(HTML) 63 Page - SPANSION

부품명 AM41DL3208G
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM41DL3208G 데이터시트(HTML) 63 Page - SPANSION

 
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62
Am41DL3208G
February 13, 2002
P R E L IMINARY
SRAM DATA RETENTION
Notes:
1. CE1#s
≥ V
CC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC.
2. Typical values are not 100% tested.
Figure 33.
CE1#s Controlled Data Retention Mode
Figure 34.
CE2s Controlled Data Retention Mode
Parameter
Symbol
Parameter Description
Test Setup
Min
Typ
Max
Unit
VDR
VCC for Data Retention
CS1#s
≥ V
CC – 0.2 V (Note 1)
1.5
3.3
V
I
DR
Data Retention Current
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
1.0
(Note 2)
15
µA
t
SDR
Data Retention Set-Up Time
See data retention waveforms
0ns
t
RDR
Recovery Time
t
RC
ns
VDR
VCC
2.7V
2.2V
CE1#s
GND
Data Retention Mode
CE1#s
VCC - 0.2 V
tSDR
tRDR
VCC
2.7 V
0.4 V
VDR
CE2s
GND
Data Retention Mode
tSDR
tRDR
CE2s < 0.2 V


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