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AD6636BBCZ1 데이터시트(PDF) 11 Page - Analog Devices |
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AD6636BBCZ1 데이터시트(HTML) 11 Page - Analog Devices |
11 / 72 page AD6636 Rev. 0 | Page 11 of 72 Name Type Pin No. Function CLKC, CLKD Input A6, A5 LVDS Differential Clock for LVDS_C Input Port (LVDS_CLKC+, LVDS_CLKC−). INA[0:15], INB[0:15] LVDS Input See Table 8 In LVDS input mode, INA[0 :15] and INB[0 :15] form a differential pair LVDS_A+[0:15] (positive node) and LVDS_A–[0:15] (negative node), respectively. INC[0:15], IND[0:15] LVDS Input See Table 8 In LVDS input mode, INC[0 :15] and IND[0 :15] form a differential pair LVDS_C+[0:15] (positive node) and LVDS_C–[0:15] (negative node), respectively. OUTPUT PORTS PCLK Bidirectional E16 Parallel Output Port Clock. Master mode output, Slave mode input. PA[0:15] Output See Table 8 Parallel Output Port A Data Bus. PACH[0:2] Output G15, D16, H12 Channel Indicator Output Port A. PAIQ Output H13 Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus. PAGAIN Output G13 Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PAACK Input H14 Parallel Port A Acknowledge (Active High). PAREQ Output F15 Parallel Port A Request (Active High). PB[0:15] Output See Table 8 Parallel Output Port B Data Bus. PBCH[0:2] Output C13, D11, B14 Channel Indicator Output Port B. PBIQ Output D12 Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus. PBGAIN Output A14 Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PBACK Input E12 Parallel Port B Acknowledge (Active High). PBREQ Output E11 Parallel Port B Request (Active High). PC[0:15] Output See Table 8 Parallel Output Port C Data Bus. PCCH[0:2] Output M15, L14, N15 Channel Indicator Output Port C. PCIQ Output P15 Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus. PCGAIN Output P16 Parallel Port C Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PCACK Input L13 Parallel Port C Acknowledge (Active High). PCREQ Output R16 Parallel Port C Request (Active High). MISC PINS RESET Input P3 Master Reset (Active Low). IRP Output T2 Interrupt Pin. SYNC[0:3] Input B12, A12, C10, B11 Synchronization Inputs. SYNC pins are independent of channels or input ports and independent of each other. LVDS_RSET Input E4 LVDS Resistor Set Pin (Analog Pin). See Design Notes. EXT_FILTER Input R4 PLL Loop Filter (Analog Pin). See Design Notes. MICROPORT CONTROL D[0:15] Bidirectional See Table 8 Bidirectional Microport Data. This bus is three-stated when CS is high. A[0:7] Input See Table 8 Microport Address Bus. DS(RD) Input P4 Active Low Data Strobe when MODE = 1. Active Low Read Strobe when MODE = 0. DTACK (RDY)1 Output M6 Active Low Data Acknowledge when MODE = 1. Microport Status Pin when MODE = 0. R/W (WR) Input N4 Read/Write Strobe when MODE = 1. Active Low Write Strobe when MODE = 0. MODE Input T3 Mode Select Pin. When SMODE = 0: Logic 0 = Intel mode; Logic 1 = Motorola mode. When SMODE = 1: Logic 0 = SPI mode; Logic 1 = SPORT mode. CS Input N5 Active Low Chip Select. Logic 1 three-states the microport data bus. CPUCLK Input R1 Microport CLK Input (Input Only). CHIPID[0:3] Input T4, R5, N6, P6 Chip ID Input Pins. |
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