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AK4132 데이터시트(PDF) 18 Page - Asahi Kasei Microsystems |
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AK4132 데이터시트(HTML) 18 Page - Asahi Kasei Microsystems |
18 / 27 page [AK4132] 015015036-E-03 2018/05 - 18 - (3) SDTO data output becomes enabled. (4) The statuses of the CM, ODIF and IDIF pins should be changed while the PDN pin= “L”. Case2: ILRCK and OLRCK are not input when the PDN pin= “H” Case 2 External clocks (Input port) SDTI SDTO (Internal state) Power-down Normal operation Ratio detection & GD < 20.2ms Normal data (No Clock) External clocks (Output port) PDN Power-down Don ’t care Don ’t care Don ’t care “0” data LDO Up Input Clocks Input Data Output Clocks “0” data (Don ’t care) (Don ’t care) (3) wait ILRCK (1) (2) (4) LDO: Internal Regurator GD: Group Delay <5ms Figure 16. System Reset Case2 Note: (1) The SDTO pin output is “L” when the PDN pin= “L”. (2) The internal regulator is powered up by PDN pin = “H” and wait for ILRCK and OLRCK. (3) SRC circuit is powered up and sampling frequency ratio detection starts when ILRCK and OLRCK are input. SDTO output starts after group delay period when the frequency ratio detection is completed. Until then, the SDTO output is “L”. The time until SDTO output becomes enabled after ILRCK and OLRCK input is 20.2msec (Max.). (4) SDTO output becomes enabled. |
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