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AM29BDS640GBC3WSI 데이터시트(PDF) 44 Page - SPANSION |
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44 / 65 page 42 Am29BDS640G 25903C1 October 1, 2003 Prelimin ary sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 5, “Toggle Bit Algorithm,” on page 41, See “DQ6: Toggle Bit I” on page 40., Figure 28, “Toggle Bit Timings (During Embedded Algorithm),” on page 65, and Table 14, “DQ6 and DQ2 Indi- cations,” on page 42. Table 14. DQ6 and DQ2 Indications Reading Toggle Bits DQ6/DQ2 Refer to Figure 4 for the following discussion. Whenever the system initially be- gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as de- scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified inter- nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. If device is and the system reads then DQ6 and DQ2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. The system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable. |
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