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DM74LS107AN 데이터시트(PDF) 1 Page - National Semiconductor (TI) |
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DM74LS107AN 데이터시트(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF6367 June 1989 DM54LS107ADM74LS107A Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs may change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic level on the clear input will reset the outputs regardless of the logic levels of the other inputs Connection Diagram Dual-In-Line Package TLF6367 – 1 Order Number DM54LS107AJ DM54LS107AW DM74LS107AM or DM74LS107AN See NS Package Number J14A M14A N14A or W14B Function Table Inputs Outputs CLR CLK J K Q Q LX X X L H H v LL Q0 Q0 H v HL H L H v LH L H H v H H Toggle HH X X Q0 Q0 H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level v e Negative going edge of pulse Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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