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ADRF6516 데이터시트(PDF) 16 Page - Analog Devices |
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ADRF6516 데이터시트(HTML) 16 Page - Analog Devices |
16 / 29 page ADRF6516 Data Sheet Rev. C | Page 16 of 29 THEORY OF OPERATION The ADRF6516 consists of a matched pair of buffered, program- mable filters followed by a cascade of two variable gain amplifiers and output ADC drivers. The block diagram of a single channel is shown in Figure 44. The programmability of the bandwidth and of the pre- and post- filtering gain through the SPI interface offers great flexibility when coping with signals of varying levels in the presence of noise and large, undesired signals nearby. The entire differential signal chain is dc-coupled with flexible interfaces at the input and output. The bandwidth and gain setting controls for the two channels are shared, ensuring close matching of their magnitude and phase responses. The ADRF6516 can be fully disabled through the ENBL pin. 3dB/6dB PREAMP 1MHz TO 31MHz PROG. FILTERS 25dB VGA 6dB/12dB ADC DRIVER BASEBAND INPUTS BASEBAND OUTPUTS GAIN AND FILTER PROGRAMMING SPI BUS ANALOG GAIN CONTROL 15mV/dB 25dB VGA OUTPUT COMMON-MODE CONTROL SPI INTERFACE Figure 44. Signal Path Block Diagram for a Single Channel of the ADRF6516 Filtering and amplification are fundamental operations in any signal processing system. Filtering is necessary to select the intended signal while rejecting out-of-band noise and inter- ferers. Amplification increases the level of the desired signal to overcome noise added by the system. When used together, filtering and amplification can extract a low level signal of interest in the presence of noise and out-of-band interferers. Such analog signal processing alleviates the requirements on the analog, mixed signal, and digital components that follow. INPUT BUFFERS The input buffers provide a convenient interface to the sensitive filter sections that follow. They set a differential input impedance of 1600 Ω and float to a common-mode voltage near VPS/2. The inputs can be dc-coupled or ac-coupled. If using direct dc coupling, the common-mode voltage presented to the inputs must be approximately VPS/2 to maximize the input swing capacity. For a 3.3 V supply, the common-mode voltage can range from 1.1 V to 1.8 V while maintaining a >65 dBc HD3 for a 400 mV p-p input signal. The VICM pin provides the optimal midsupply common-mode voltage and can be used as a refer- ence for the driving circuit. The VICM voltage is not buffered and must be sensed at a high impedance point to prevent it from being loaded down. The input buffers in both channels can be configured simul- taneously for a gain of 3 dB or 6 dB through the SPI (see the Register Map and Codes section). When configured for a 3 dB gain, the buffers support a 400 mV p-p differential input level with ~70 dBc harmonic distortion. For a 6 dB gain setting, the buffers support 280 mV p-p inputs. PROGRAMMABLE FILTERS The integrated programmable filter is the key signal processing function in the ADRF6516. The filters follow a six-pole Butter- worth prototype response that provides a compromise between band rejection, ripple, and group delay. The 0.5 dB bandwidth is programmed from 1 MHz to 31 MHz in 1 MHz steps via the serial programming interface (SPI), as described in the Programming the Filters and Gains section. The filters are designed so that the Butterworth prototype filter shape and group delay responses vs. frequency are retained for any bandwidth setting. Figure 45 and Figure 46 illustrate the ideal six-pole Butterworth magnitude and group delay responses, respectively. The group delay, τg, is defined as τg = −∂φ/∂ω where: φ is the phase in radians. ω = 2πf (the frequency in radians/sec). Note that for a frequency scaled filter prototype, the absolute magnitude of the group delay scales inversely with the band- width; however, the shape is retained. For example, the peak group delay for a 28 MHz bandwidth setting is 14× less than for a 2 MHz setting (see Figure 46). 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 1M 10M 100M 1G FREQUENCY (Hz) Figure 45. Sixth-Order Butterworth Magnitude Response for 0.5 dB Bandwidths Programmed from 2 MHz to 29 MHz in 1 MHz Steps |
유사한 부품 번호 - ADRF6516_17 |
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유사한 설명 - ADRF6516_17 |
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