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๋ถ€ํ’ˆ๋ช… MSP430F2101
์ƒ์„ธ๋‚ด์šฉ  MIXED SIGNAL MICROCONTROLLER
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MSP430F2101 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Texas Instruments

 
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MSP430x21x1
MIXED SIGNAL MICROCONTROLLER
SLAS439C โˆ’ SEPTEMBER 2004 โˆ’ REVISED JULY 2006
2
POST OFFICE BOX 655303
โ€ข DALLAS, TEXAS 75265
device pinout
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
Note: NC pins not internally connected
Power Pad connection to VSS recommended
10
1
9
7
8
6
5
4
3
2
11
20
12
14
13
15
16
17
18
19
TEST
VCC
P2.5/CA5
VSS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
P2.3/TA1/CA0
P1.4/SMCLK/TCK
1
6
5
4
3
2
18
13
14
15
16
17
712
11
10
9
8
19
24 23 22 21 20
VSS
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI
P2.0/ACLK/CA2
P1.5/TA0/TMS
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P1.4/SMCLK/TCK
NC
functional block diagram
Basic Clock
System+
RAM
256B
256B
128B
128B
Brownout
Protection
RST/NMI
VCC
VSS
MCLK
SMCLK
Watchdog
WDT+
15/16โˆ’Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
8kB
4kB
2kB
1kB
ACLK
XIN
Port P1
8I/O
Interrupt
capability,
pullโˆ’up/down
resistors
Comparator
_A+
8 Channel
Input Mux
P1.x & JTAG
8
P2.x &
XIN/XOUT
8
Port P2
8 I/O
Interrupt
capability,
pullโˆ’up/down
resistors
MDB
MAB
NOTE: See port schematics section for detailed I/O information.


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