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CDCM1802RGTR 데이터시트(PDF) 4 Page - Texas Instruments

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부품명 CDCM1802RGTR
상세설명  CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O ADDITIONAL LVCMOS OUTPUT
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CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control pin settings
The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings.
All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place
them into a high-z (or tristate) output state when pulled to GND.
RS0 = Open
EN
CDCM1802
S1
S0
RS1 = 0
REN = 60 kΩ
Setting for Mode 4:
EN = VDD/2
S1 = 0
S0 = 1
Figure 1. Control Pin Setting for Example
Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing
a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.
Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to
VDD/2, the installed resistor needs a value of 60 kΩ with a tolerance better or equal to 10%.
Table 1. Selection Mode Table
LVPECL
LVCMOS
MODE
EN
S1
S0
Y0
Y1
0
0
X
X
Off (high-z)
Off (high-z)
1
VDD/2
0
VDD/2
÷ 1
÷ 1
2
VDD/2
VDD/2
1
÷ 1
÷ 2
3
1
0
0
÷ 1
÷ 4
4
VDD/2
0
1
÷ 2
÷ 2
5
1
0
1
÷ 2
÷ 4
6
VDD/2
0
0
÷ 4
÷ 4
7
VDD/2
1
0
÷ 4
÷ 8
8
VDD/2
VDD/2
VDD/2
÷ 8
÷ 1
9
1
1
0
÷ 8
÷ 4
10
1
1
1
Off (high-z)
÷ 4
NOTE: The LVPECL outputs are open emitter stages. Thus, if you leave the unused
LVPECL output Y0 unconnected, then the current consumption is minimized and
noise impact to remaining outputs is neglectable. Also, each output can be
individually disabled by connecting the corresponding VDD input to GND.


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