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CDCM1802RGTT 데이터시트(PDF) 6 Page - Texas Instruments |
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CDCM1802RGTT 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 22 page CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER tpd(lh) Propagation delay rising edge VOX to VOX 320 600 ps tpd(hl) Propagation delay falling edge VOX to VOX 320 600 ps tsk(p) LVPECL pulse skew, See Note B in Figure 8 VOX to VOX 100 ps NOTES: 1. Is required to maintain ac specifications 2. Is required to maintain device functionality 3. For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal. LVCMOS OUTPUT PARAMETER, Y1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fclk Output frequency, see Note 4 and Figure 5 0 200 MHz tskLVCMOS(o) Output skew between the LVCMOS output Y1 and LVPECL output Y0 VOX to VDD/2, See Figure 8 1.6 ns tsk(pp) Part-to-part skew Y1, See Note A in Figure 8 300 ps VDD = min to max, IOH = −100 µA VDD–0.1 VOH High-level output voltage VDD = 3 V, IOH = −6 mA 2.4 V VOH High level output voltage VDD = 3 V, IOH = −12 mA 2 V VDD = min to max, IOL=100 µA 0.1 VOL Low-level output voltage VDD = 3 V, IOL = 6 mA 0.5 V VOL Low level output voltage VDD = 3 V, IOL = 12 mA 0.8 V IOH High-level output current VDD = 3.3 V, VO = 1.65 V −29 mA IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 37 mA IOZ High-impedance state output current VDD = 3.6 V, VO = VDD or 0 V ±5 µA CO Output capacitance VDD = 3.3 V 2 pF Load Expected output loading, see Figure 10 10 pF tDuty Output duty cycle distortion, see Note 5 Measured at VDD/2 −150 150 ps tpd(lh) Propagation delay rising edge from IN to Y1 VOX to VDD/2 load, see Figure 10 1.6 2.6 ns tpd(hl) Propagation delay falling edge from IN to Y1 VOX to VDD/2 load, see Figure 10 1.6 2.6 ns tr Output rise slew rate 20% to 80% of swing, see Figure 10 1.4 2.3 V/ns tf Output fall slew rate 80% to 20% of swing, see Figure 10 1.4 2.3 V/ns NOTES: 4. Operating the CDCM1802 LVCMOS output above the maximum frequency will not cause a malfunction to the device, but the Y1 output signal swing will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1802 can be operated at higher frequencies, while the LVCMOS output Y1 becomes unusable. 5. For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal. |
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