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TC58NS256DC 데이터시트(HTML) 4 Page - Toshiba Semiconductor

부품명 TC58NS256DC
상세내용  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ®8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)
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제조사  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TC58NS256DC 데이터시트(HTML) 4 Page - Toshiba Semiconductor

 
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TC58NS256DC
2000-08-27
4/33
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
==== 0°~55°C, VCC ==== 3.3 V ±±±± 0.3 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
tCLS
CLE Setup Time
0
ns
tCLH
CLE Hold Time
10
ns
tCS
CE Setup Time
0
ns
tCH
CE Hold Time
10
ns
tWP
Write Pulse Width
25
ns
tALS
ALE Setup Time
0
ns
tALH
ALE Hold Time
10
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
10
ns
tWC
Write Cycle Time
50
ns
tWH
WE -High Hold Time
15
ns
tWW
WP High to WE Low
100
ns
tRR
Ready-to-
RE Falling Edge
20
ns
tRP
Read Pulse Width
35
ns
tRC
Read Cycle Time
50
ns
tREA
RE Access Time (Serial Data Access)
35
ns
tCEH
CE -High Time for Last Address in Serial Read Cycle
100
ns
(2)
tREAID
RE Access Time (ID Read)
35
ns
tOH
Data Output Hold Time
10
ns
tRHZ
RE -High-to-Output-High Impedance
30
ns
tCHZ
CE -High-to-Output-High Impedance
20
ns
tREH
RE -High Hold Time
15
ns
tIR
Output-High-Impedance-to-
RE Rising Edge
0
ns
tRSTO
RE Access Time (Status Read)
35
ns
tCSTO
CE Access Time (Status Read)
45
ns
tRHW
RE High to WE Low
0
ns
tWHC
WE High to CE Low
30
ns
tWHR
WE High to RE Low
30
ns
tAR1
ALE Low to
RE Low (ID Read)
100
ns
tCR
CE Low to
RE Low (ID Read)
100
ns
tR
Memory Cell Array to Starting Address
25
µs
tWB
WE High to Busy
200
ns
tAR2
ALE Low to
RE Low (Read Cycle)
50
ns
tRB
RE Last Clock Rising Edge to Busy (in Sequential Read)
200
ns
tCRY
CE High to Ready (When interrupted by CE in Read Mode)
600
+ tr
(
BY
/
RY
)
ns
(1)
tRST
Device Reset Time (Read/Program/Erase)
6/10/500
µs
AC TEST CONDITIONS
PARAMETER
VALUES
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3 ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
Output load
CL (100 pF) + 1 TTL


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