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TC58NS256DC 데이터시트(PDF) 19 Page - Toshiba Semiconductor

부품명 TC58NS256DC
상세설명  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M 짰8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC58NS256DC 데이터시트(HTML) 19 Page - Toshiba Semiconductor

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TC58NS256DC
2000-08-27
19/33
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte
527.
Sequential Read (1) (2) (3)
This mode allows the sequential reading of pages without additional address input.
Sequential Read modes (1) and (2) output the contents of addresses 0~527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last
address, the device continues to output the data from this address ** on each RE clock signal.
** Column address 527 on the last page.
BY
/
RY
WE
CLE
RE
Busy
50H
CE
ALE
I/O
Figure 5. Read mode (3) operation
527
Addresses bits A0~A3 are used to set the start pointer for the
redundant memory cells, while A4~A7 are ignored.
Once a 50H command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address. (An
00H command is necessary to move the pointer back to the
0-to-511 main memory cell location.)
512
A0~A3
A
Sequential Read (1)
(00H)
0
527
A
Sequential Read (2)
(01H)
A
Sequential Read (3)
(50H)
512 527
BY
/
RY
00H
Busy
01H
Busy
Busy
Address input
tR
Data output
50H
Data output
tR
tR


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