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TC58NS256DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 30 Page - Toshiba Semiconductor

๋ถ€ํ’ˆ๋ช… TC58NS256DC
์ƒ์„ธ๋‚ด์šฉ  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ยฎ8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)
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์ œ์กฐ์‚ฌ  TOSHIBA [Toshiba Semiconductor]
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TC58NS256DC ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 30 Page - Toshiba Semiconductor

 
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TC58NS256DC
2000-08-27
30/33
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 10 segments. Each segment can be programmed individually as follows:
(13)
Note regarding the RE signal
The internal column address counter is incremented synchronously with the RE clock in Read mode.
Therefore, once the device has been set to Read mode by a 00H, 01H or 50H command, the internal column
address counter is incremented by the RE clock independently of the address input timing. If the RE
clock input pulses start before the address input, and the pointer reaches the last column address, an
internal read operation (array โ†’ register) will occur and the device will enter Busy state. (Refer to Figure
25.)
Hence the RE clock input must start after the address input.
Figure 25.
Address input
WE
I/O
BY
/
RY
RE
00H/01H/50H
Data Pattern 10
Data Pattern 1
All 1s
Figure 24.
Note: The input data for unprogrammed or previously programmed page segments must be 1
(i.e. the inputs for all page bytes outside the segment which is to be programmed should
be set to all 1).
First programming
Second programming
Tenth programming
Result
Data Pattern 1
Data Pattern 10
Data Pattern 2
All 1s
All 1s
Data Pattern 2
All 1s


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