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MB84VD23381FJ 데이터시트(HTML) 35 Page - Fujitsu Component Limited.

부품명 MB84VD23381FJ
상세내용  Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
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제조사  FUJITSU [Fujitsu Component Limited.]
홈페이지  http://edevice.fujitsu.com/fmd/en/index.html
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MB84VD23381FJ 데이터시트(HTML) 35 Page - Fujitsu Component Limited.

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MB84VD23381FJ-80
34
s
s
s
s 64 M FCRAM AC Charactaristics for MCP
•••• READ OPERATION (FCRAM)
*1: The output load is 30 pF.
*2: The output load is 5 pF.
*3: The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
*4: Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access.
*5: Applicable if OE is brought to Low before CE1r goes Low.
*6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1r stays Low) , the tOE becomes tOE (Max)
+ tASO (Min) − tASO (actual) .
*7: The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
*8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
− tCLOL (actual) or tRC (Min) − tOP (actual) .
*9: Maximum value is applicable if CE1r is kept at Low.
Parameter
Symbol
Value
Unit
Notes
Min
Max
Read Cycle Time
tRC
90
ns
Chip Enable Access Time
tCE
80
ns
*1, *3
Output Enable Access Time
tOE
45
ns
*1
Chip Enable Access Time
tAA
80
ns
*1, *4
Output Data Hold Time
tOH
5
ns
*1
CE1r Low to Output Low-Z
tCLZ
5
ns
*2
OE Low to Output Low-Z
tOLZ
0
ns
*2
CE1r High to Output High-Z
tCHZ
30
ns
*2
OE High to Output High-Z
tOHZ
25
ns
*2
Address Setup Time to CE1r Low
tASC
−5
ns
*5
Address Setup Time to OE
tASO
45
ns
*3, *6
tASO[ABS]
10
ns
*7
Address Invalid Time
tAX
5ns
*4
CE1r Low to Address Hold Time
tCLAH
90
ns
*4
OE Low to Address Hold Time
tOLAH
45
ns
*4, *8
CE1r High to Address Hold Time
tCHAH
−5
ns
OE High to Address Hold Time
tOHAH
–5
ns
CE1r Low to OE Low Delay Time
tCLOL
45
1000
ns
*4, *6, *8, *9
OE Low to CE1r High Delay Time
tOLCH
45
ns
*8
CE1r High Pulse Width
tCP
20
ns
OE High Pulse Width
tOP
45
1000
ns
*6, *8, *9
tOP[ABS]
20
ns
*7


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