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MB84VD23381FJ 데이터시트(HTML) 36 Page - Fujitsu Component Limited.

부품명 MB84VD23381FJ
상세내용  Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
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제조사  FUJITSU [Fujitsu Component Limited.]
홈페이지  http://edevice.fujitsu.com/fmd/en/index.html
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MB84VD23381FJ 데이터시트(HTML) 36 Page - Fujitsu Component Limited.

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MB84VD23381FJ-80
35
• WRITE OPERATION (FCRAM)
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
*2: New write address is valid from either CE1r or WE that is brought to High.
*3: Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High.
*4: The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stays Low.
*6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
*7: Applicable if CE1r stays Low after read operation.
*8: tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively.
*9: tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively.
The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
Parameter
Symbol
Value
Unit
Notes
Min
Max
Write Cycle Time
tWC
90
ns
*1
Address Setup Time
tAS
0
ns
*2
Address Hold Time
tAH
45
ns
*2
CE1r Write Setup Time
tCS
0
1000
ns
CE1r Write Hold Time
tCH
0
1000
ns
WE Setup Time
tWS
0
ns
WE Hold Time
tWH
0
ns
LB and UB Setup Time
tBS
0
ns
LB and UB Hold Time
tBH
−5
ns
OE Setup Time
tOES
0
1000
ns
*3
OE Hold Time
tOEH
45
1000
ns
*3, *4
tOEH[ABS]
20
ns
*5
OE High to CE1r Low Setup Time
tOHCL
−3
ns
*6
OE High to Address Hold Time
tOHAH
−5
ns
*7
CE1r Write Pulse Width
tCW
60
ns
*1, *8
WE Write Pulse Width
tWP
60
ns
*1, *8
CE1r Write Recovery Time
tWRC
15
ns
*1, *9
WE Write Recovery Time
tWR
15
1000
ns
*1, *3, *9
Data Setup Time
tDS
20
ns
Data Hold Time
tDH
0
ns
CE1r High Pulse Width
tCP
20
ns
*9


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