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MB84VD23381FJ ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Fujitsu Component Limited.

๋ถ€ํ’ˆ๋ช… MB84VD23381FJ
์ƒ์„ธ๋‚ด์šฉ  Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
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์ œ์กฐ์‚ฌ  FUJITSU [Fujitsu Component Limited.]
ํ™ˆํŽ˜์ด์ง€  http://edevice.fujitsu.com/fmd/en/index.html
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MB84VD23381FJ ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Fujitsu Component Limited.

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MB84VD23381FJ-80
5
s
s
s
s PIN DESCRIPTION
s
s
s
s BLOCK DIAGRAM
Pin Name
Function
Input/Output
A19 to A0
Address Inputs (Common)
I
A21, A20
Address Inputs (Flash)
I
DQ15 to DQ0
Data Inputs/Outputs (Common)
I/O
CEf
Chip Enable (Flash)
I
CE1r
Chip Enable (FCRAM)
I
CE2r
Chip Enable (FCRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
RY/BY
Ready/Busy Outputs (Flash) Open Drain Output
O
UB
Upper Byte Control (FCRAM)
I
LB
Lower Byte Control (FCRAM)
I
RESET
Hardware Reset Pin/Sector Protection Unlock (Flash)
I
WP/ACC
Write Protect/Acceleration (Flash)
I
N.C.
No Internal Connection
๏ฃง
VSS
Device Ground (Common)
Power
VCCf
Device Power Supply (Flash)
Power
VCCr
Device Power Supply (FCRAM)
Power
VSS
VCCr
64 M bit
RESET
Flash Memory
WE
16 M bit
FCRAM
CEf
A21 to A0
OE
CE1r
VSS
VCCf
A21 to A0
A19 to A0
DQ15 to DQ0
RY/BY
LB
UB
WP/ACC
CE2r
DQ15 to DQ0
DQ15 to DQ0


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