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DAC5686 데이터시트(PDF) 27 Page - Texas Instruments |
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DAC5686 데이터시트(HTML) 27 Page - Texas Instruments |
27 / 46 page www.ti.com Interleave Bus Mode IOUTB1 IOUTB2 IOUTA1 IOUTA2 16-Bit DAC 2Fdata 2 – 16 y Fdata Fdata y2 16-Bit DAC 2Fdata y2 FIR1 Edge Triggered Input Latches • •• • •• DA[15:0] DEMUX DA[15:0] ts(DATA) th(DATA) A0 B0 A1 AN BN B1 TxENABLE ts(TxENABLE) CLK1 or PLLLOCK DAC5686 SLWS147B – APRIL 2003 – REVISED AUGUST 2004 In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 31 shows the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 32. Figure 31. Interleave Bus Mode Data Path Figure 32. Interleave Bus Mode Timing Diagram Using TxENABLE Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels A and B can be synchronized using either the QFLAG pin or the TxENABLE pin. When qflag in register config_usb is 0, transitions on TxENABLE identify the interleaved data sequence. The first data after the rising edge of TxENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an output to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 33). 27 |
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