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S71GL032A ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71GL032A
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
Advance
Info rmation
Erase and Program Operations-S29GL064A Only .................................. 70
Figure 16. Program Operation Timings .................................. 72
Figure 17. Accelerated Program Timing Diagram .................... 72
Figure 18. Chip/Sector Erase Operation Timings..................... 73
Figure 19. Data# Polling Timings
(During Embedded Algorithms) ............................................ 73
Figure 20. Toggle Bit Timings (During Embedded Algorithms) .. 74
Figure 21. DQ2 vs. DQ6 ...................................................... 74
Temporary Sector Unprotect .........................................................................75
Figure 22. Temporary Sector Group Unprotect Timing Diagram 75
Figure 23. Sector Group Protect and Unprotect Timing Diagram 76
Alternate CE# Controlled Erase and
Program Operations-S29GL064A ..................................................................77
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .............................................................. 79
Erase And Programming Performance . . . . . . . .80
Type 4 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Functional Description . . . . . . . . . . . . . . . . . . . . . 81
Product Portfolio ................................................................................................ 81
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 82
Operating Range ................................................................................................. 82
Table 25. DC Electrical Characteristics
(Over the Operating Range) ............................................... 82
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . 83
AC Test Loads and Waveforms . . . . . . . . . . . . . 83
Figure 25. AC Test Loads and Waveforms.............................. 83
Table 26. Switching Characteristics ...................................... 84
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 85
Figure 26. Read Cycle 1 (Address Transition Controlled).......... 85
Figure 27. Read Cycle 2 (OE# Controlled) ............................. 85
Figure 28. Write Cycle 1 (WE# Controlled) ............................ 86
Figure 29. Write Cycle 2 (CE#1 or CE2 Controlled) ................. 87
Figure 30. Write Cycle 3 (WE# Controlled, OE# Low).............. 88
Figure 31. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low).... 88
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 27. Truth Table ......................................................... 89
Type 1 SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 90
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Functional Description . . . . . . . . . . . . . . . . . . . . . . 91
4M Version F, 4M version G, 8M version C ...........................................91
Byte Mode ..............................................................................................................91
Functional Description . . . . . . . . . . . . . . . . . . . . . 92
8M Version D ..................................................................................................92
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 93
Recommended DC Operating Conditions (Note 1) ............................... 93
Capacitance (f=1MHz, TA=25ยฐC) ................................................................... 93
DC Operating Characteristics ....................................................................... 93
Common ........................................................................................................... 93
DC Operating Characteristics .......................................................................94
4M Version F ...................................................................................................94
DC Operating Characteristics .......................................................................94
4M Version G ..................................................................................................94
DC Operating Characteristics ....................................................................... 95
8M Version C .................................................................................................. 95
DC Operating Characteristics ....................................................................... 95
8M Version D .................................................................................................. 95
AC Operating Conditions . . . . . . . . . . . . . . . . . . . 96
Test Conditions ..................................................................................................96
Figure 32. AC Output Load.................................................. 96
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 96
Read/Write Characteristics (VCC=2.7-3.3V) ..............................................96
Data Retention Characteristics (4M Version F) ....................................... 97
Data Retention Characteristics (4M Version G) ......................................98
Data Retention Characteristics (8M Version C) ......................................98
Data Retention Characteristics (8M Version D) ......................................98
Timing Diagrams .................................................................................................98
Figure 33. Timing Waveform of Read Cycle(1) (Address Controlled,
CS#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) ........ 98
Figure 34. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE#
is Low, Ignore UB#/LB# Timing) ......................................... 99
Figure 35. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing) ............................... 99
Figure 36. Timing Waveform of Write Cycle(2) (CS# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing) ............................. 100
Figure 37. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled)...................................................................... 100
Figure 38. Data Retention Waveform.................................. 101
Revision Summary


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