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S71GL032A 데이터시트(HTML) 98 Page - SPANSION

부품명 S71GL032A
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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S71GL032A 데이터시트(HTML) 98 Page - SPANSION

 
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98
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
Advance
Info rmation
Data Retention Characteristics (4M Version G)
Notes:
1. CS1 controlled:CS1#
VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
Data Retention Characteristics (8M Version C)
Notes:
1. CS1 controlled:CS1#
VCC-0.2V. CS2 controlled: CS2 0.2V.
Data Retention Characteristics (8M Version D)
Notes:
1. CS1 controlled:CS1#
VCC-0.2V. CS2 controlled: CS2 0.2V.
Timing Diagrams
Item
Symbol
Test Condition
Min
Typ
Max Unit
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V. BYTE# = VSS or VCC 1.5
-
3.3
V
Data retention current
IDR
VCC=1.5V, CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V
-
-
3
µA
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
Item
Symbol
Test Condition
Min
Typ
Max Unit
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1). BYTE# = VSS or VCC
1.5
-
3.3
V
Data retention current
IDR
VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1)
-
-
15
µA
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
Item
Symbol
Test Condition
Min
Typ
Max Unit
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1), BYTE# = VSS or VCC
1.5
-
3.3
V
Data retention current
IDR
VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1)
-
-
TBD
µA
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
Figure 33. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB#
and/or LB#=VIL)
tAA
tRC
tOH
Address
Data Out
Previous Data Valid
Data Valid


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