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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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S71PL129Jxx_00_A5 December 23, 2004
Advance
Info rmation
Table 14. Write Operation Status ......................................... 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62
Figure 8. Maximum Overshoot Waveforms............................. 62
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .63
Industrial (I) Devices ..........................................................................................63
Extended (E) Devices .........................................................................................63
Supply Voltages ....................................................................................................63
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 15. CMOS Compatible ................................................ 64
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
Test Conditions ...................................................................................................65
Figure 9. Test Setups......................................................... 65
Table 16. Test Specifications ............................................... 65
Switching Waveforms ........................................................................................65
Table 17. Key to Switching Waveforms ................................. 65
Figure 10. Input Waveforms and Measurement Levels............. 66
VCC RampRate .................................................................................................. 66
Read Operations ................................................................................................ 66
Table 18. Read-Only Operations .......................................... 66
Figure 11. Read Operation Timings....................................... 67
Figure 12. Page Read Operation Timings ............................... 67
Reset ...................................................................................................................... 68
Table 19. Hardware Reset (RESET#) .................................... 68
Figure 13. Reset Timings..................................................... 68
Erase/Program Operations ............................................................................. 69
Table 20. Erase and Program Operations .............................. 69
Timing Diagrams ................................................................................................. 70
Figure 14. Program Operation Timings .................................. 70
Figure 15. Accelerated Program Timing Diagram .................... 70
Figure 16. Chip/Sector Erase Operation Timings..................... 71
Figure 17. Back-to-back Read/Write Cycle Timings ................. 72
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 72
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 73
Figure 20. DQ2 vs. DQ6 ...................................................... 73
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 21. Temporary Sector Unprotect ................................. 74
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 74
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 75
Controlled Erase Operations ..........................................................................76
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 76
Table 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 77
Table 24. CE1#/CE2# Timing ............................................. 77
Figure 23. Timing Diagram for Alternating Between CE1# and CE2#
Control ............................................................................. 78
Table 25. Erase And Programming Performance .................... 78
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 78
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional Description . . . . . . . . . . . . . . . . . . . . . 80
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 80
AC Characteristics and Operating Conditions . 81
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 82
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .83
Read Timings ........................................................................................................83
Figure 24. Read Cycle ......................................................... 83
Figure 25. Page Read Cycle (8 Words Access) ........................ 84
Write Timings ......................................................................................................85
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 85
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 86
Deep Power-down Timing ..............................................................................86
Figure 28. Deep Power Down Timing .................................... 86
Power-on Timing ................................................................................................86
Figure 29. Power-on Timing ................................................ 86
Provisions of Address Skew ............................................................................87
Read ....................................................................................................................87
Figure 30. Read................................................................. 87
Write ..................................................................................................................87
Figure 31. Write ................................................................ 87
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 88
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 88
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .89
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 94
Output Load Circuit .......................................................................................... 95
Figure 32. Output Load Circuit............................................. 95
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 95
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107
Read Cycle ...........................................................................................................107
Figure 33. Timing of Read Cycle
(CE# = OE# = VIL, WE# = ZZ# = VIH).............................. 107
Figure 34. Timing Waveform of Read Cycle
(WE# = ZZ# = VIH)......................................................... 108
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = VIH)......................................................... 109
Write Cycle ..........................................................................................................110
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = VIH)................................................ 110
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = VIH)................................................. 110
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = VIH) ................................................................... 111
Partial Array Self Refresh (PAR) .....................................................................111
Temperature Compensated Refresh (for 64Mb) .....................................112
Deep Sleep Mode ...............................................................................................112
Reduced Memory Size (for 32M and 16M) ..................................................112
Other Mode Register Settings (for 64M) ....................................................112
Figure 39. Mode Register.................................................. 113
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are
Donโ€™t Care)..................................................................... 113
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 114
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 114
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Product Information . . . . . . . . . . . . . . . . . . . . . . 118
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 119
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119
Power Up ..............................................................................................................119
Figure 43. Power Up 1 (CS1# Controlled) ........................... 119
Figure 44. Power Up 2 (CS2 Controlled).............................. 119
Functional Description . . . . . . . . . . . . . . . . . . . . 120
Absolute Maximum Ratings . . . . . . . . . . . . . . . 120
DC Recommended Operating Conditions . . . . 120


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