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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 47 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71PL129JC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 47 Page - SPANSION

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June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
47
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Informatio n
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the Secured
Silicon Sector, autoselect and CFI functions are unavailable when the Secured Sil-
icon Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from โ€œ0โ€ back to a โ€œ1.โ€ Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read shows that the data is
still โ€œ0.โ€ Only erase operations can convert a โ€œ0โ€ to a โ€œ1.โ€
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster
than using the standard program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h. That bank then
enters the unlock bypass mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time. Table 12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (Table 13)
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
be at VHH any operation other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
Figure 4 illustrates the algorithm for the program operation. See the Erase/Pro-
gram Operations table in AC Characteristics for parameters, and Figure 14 for
timing diagrams.


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