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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 49 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71PL129JC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
49
Advance
Informatio n
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 12 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 ยตs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 ยตs, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. If any com-
mand other than 30h, B0h, F0h is input during the time-out period, the
normal operation cannot be guaranteed. The system must rewrite the com-
mand sequence and any additional addresses and commands. Note that Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See โ€œDQ3: Sector Erase Timerโ€ on page 61). The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See โ€œWrite Operation Statusโ€ on
page 56 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program
Operations tables in AC Characteristics for parameters, and Figure 16 for timing
diagrams.


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