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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 57 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71PL129JC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
57
Advance
Informatio n
During the Embedded Erase algorithm, Data# Polling produces a โ€œ0โ€ on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a โ€œ1โ€ on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 400 ยตs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15โ€“DQ0 on the following read cycles. Just prior to the
completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ15โ€“DQ0 while Output Enable (OE#) is asserted low. That is,
the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15โ€“DQ0 may be still invalid. Valid
data on DQ15โ€“DQ0 appears on successive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm. Figure 18 in AC Characteristics shows the Data# Polling timing
diagram.


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