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S71PL129JC0 데이터시트(HTML) 59 Page - SPANSION

부품명 S71PL129JC0
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory
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S71PL129JC0 데이터시트(HTML) 59 Page - SPANSION

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June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
59
Advance
Informatio n
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 400 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see “DQ7: Data# Polling” on page 56).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit
algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing di-
agrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical
form. See also “DQ2: Toggle Bit II”.
Figure 7. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle?
Read Byte Twice
(DQ7–DQ0)
Address = VA
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA


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