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S71PL129JC0 데이터시트(HTML) 68 Page - SPANSION

부품명 S71PL129JC0
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory
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S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
Advance
Info rmation
Reset
Note: Not 100% tested.
Table 19. Hardware Reset (RESET#)
Parameter
Description
All Speed Options
Unit
JEDEC
Std
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#
Figure 13. Reset Timings
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB


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