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S71PL129JC0 데이터시트(PDF) 69 Page - SPANSION

부품명 S71PL129JC0
부품 상세설명  Stacked Multi-Chip Product (MCP) Flash Memory
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June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
69
Advance
Informatio n
Erase/Program Operations
Notes:
1. Not 100% tested.
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#).
4. See Table 25, “Erase And Programming Performance,” on page 78 for more information.
Table 20. Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
55
60
65
70
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
55
60
65
70
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
ns
tWLAX
tAH
Address Hold Time
Min
30
35
ns
tAHT
Address Hold Time From CE1#, CE#2 or OE# high
during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
25
30
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
10
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE1# or CE#2 Setup Time
Min
0
ns
tWHEH
tCH
CE1# or CE#2 Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
20
25
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWHWH1
tWHWH1 Programming Operation (Note 4)
Typ
6
µs
tWHWH1
tWHWH1 Accelerated Programming Operation (Note 4)
Typ
4
µs
tWHWH2
tWHWH2 Sector Erase Operation (Note 4)
Typ
0.5
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
Min
35
ns


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