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S71PL129JC0 데이터시트(HTML) 73 Page - SPANSION

부품명 S71PL129JC0
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory
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June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
73
Advance
Informatio n
Notes:
1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or
CE# to toggle DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
OE#
CE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read)
(second read)
(stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing


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