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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 78 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
Advance
Info rmation
Notes:
1. Typical program and erase times assume the following conditions: 25ยฐC, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90ยฐC, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25ยฐC, f = 1.0 MHz.
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Table 25. Erase And Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.5
2
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
PL129J
135
216
sec
Word Program Time
6
100
ยตs
Excludes system level
overhead (Note 5)
Accelerated Word Program Time
4
60
ยตs
Chip Program Time
(Note 3)
PL129J
50.4
200
sec
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6.3
7
pF
COUT
Output Capacitance
VOUT = 0
7.0
8
pF
CIN2
Control Pin Capacitance
VIN = 0
5.5
8
pF
CIN3
WP#/ACC Pin Capacitance
VIN = 0
11
12
pF
CE1#
tCCR
tCCR
CE2#


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