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S71PL129JC0 데이터시트(HTML) 81 Page - SPANSION

부품명 S71PL129JC0
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory
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S71PL129JC0 데이터시트(HTML) 81 Page - SPANSION

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Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
81
Advance
Informatio n
DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)
Capacitance (Ta = 25°C, f = 1 MHz)
Note: This parameter is sampled periodically and is not 100% tested.
AC Characteristics and Operating Conditions
(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)
Symbol
Parameter
Test Condition
Min
Typ.
Max
Unit
IIL
Input Leakage
Current
VIN = 0 V to VDD
-1.0
+1.0
µA
ILO
Output Leakage
Current
Output disable, VOUT = 0 V to VDD
-1.0
+1.0
µA
VOH
Output High Voltage
IOH = - 0.5 mA
2.0
¾
V
V
VOL
Output Low Voltage
IOL = 1.0 mA
0.4
V
IDDO1 Operating Current
CE1#= VIL, CE2 = VIH, IOUT = 0
mA, tRC = min.
ET5UZ8A-43DS
40
mA
ET5VB5A-43DS
50
IDDO2
Page Access
Operating Current
CE1#= VIL, CE2 = VIH, IOUT = 0 mA
Page add. cycling, tRC = min.
25
mA
IDDS
Standby Current
(MOS)
CE1# = VDD - 0.2 V,
CE2 = VDD - 0.2 V
ET5UZ8A-43DS
70
mA
ET5VB5A-43DS
100
µA
IDDSD
Deep Power-down
Standby Current
CE2 = 0.2 V
5
µA
Symbol
Parameter
Test Condition
Max
Unit
CIN
Input Capacitance
VIN = GND
10
pF
COUT
Output Capacitance
VOUT = GND
10
pF
Symbol
Parameter
Min
Max
Unit
tRC
Read Cycle Time
70
10000
ns
tACC
Address Access Time
70
ns
tCO
Chip Enable (CE1#) Access Time
70
ns
tOE
Output Enable Access Time
25
ns
tBA
Data Byte Control Access Time
25
ns
tCOE
Chip Enable Low to Output Active
10
ns
tOEE
Output Enable Low to Output Active
0
ns
tBE
Data Byte Control Low to Output Active
0
ns
tOD
Chip Enable High to Output High-Z
20
ns
tODO
Output Enable High to Output High-Z
20
ns
tBD
Data Byte Control High to Output High-Z
20
ns


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