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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 82 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71PL129JC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 82 Page - SPANSION

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82
pSRAM Type 6
pSRAM_Type06_14_A1 Ocotober 16, 2004
Advance
Info rmation
AC Test Conditions
tOH
Output Data Hold Time
10
โ€”
ns
tPM
Page Mode Time
70
10000
ns
tPC
Page Mode Cycle Time
30
โ€”
ns
tAA
Page Mode Address Access Time
โ€”
30
ns
tAOH
Page Mode Output Data Hold Time
10
โ€”
ns
tWC
Write Cycle Time
70
10000
ns
tWP
Write Pulse Width
50
โ€”
ns
tCW
Chip Enable to End of Write
70
โ€”
ns
tBW
Data Byte Control to End of Write
60
โ€”
ns
tAW
Address Valid to End of Write
60
โ€”
ns
tAS
Address Set-up Time
0
โ€”
ns
tWR
Write Recovery Time
0
โ€”
ns
tCEH
Chip Enable High Pulse Width
10
โ€”
ns
tWEH
Write Enable High Pulse Width
6
โ€”
ns
tODW
WE# Low to Output High-Z
โ€”
20
ns
tOEW
WE# High to Output Active
0
ns
tDS
Data Set-up Time
30
โ€”
ns
tDH
Data Hold Time
0
โ€”
ns
tCS
CE2 Set-up Time
0
โ€”
ns
tCH
CE2 Hold Time
300
โ€”
ยตs
tDPD
CE2 Pulse Width
10
โ€”
ms
tCHC
CE2 Hold from CE1#
0
โ€”
ns
tCHP
CE2 Hold from Power On
30
โ€”
ยตs
Parameter
Condition
Output load
30 pF + 1 TTL Gate
Input pulse level
VDD - 0.2 V, 0.2 V
Timing measurements
VDD x 0.5
Reference level
VDD x 0.5
tR, tF
5 ns
Symbol
Parameter
Min
Max
Unit


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