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S71PL129JC0 데이터시트(HTML) 87 Page - SPANSION

부품명 S71PL129JC0
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory
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S71PL129JC0 데이터시트(HTML) 87 Page - SPANSION

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Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
87
Advance
Informatio n
Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than tRC min. sustain over 10 µs
in an active status, at least one valid address cycle over tRC min. is required dur-
ing 10µs.
Write
In case multiple invalid address cycles shorter than tWC min. sustain over 10 µs
in an active status, at least one valid address cycle over tWC min. is required dur-
ing 10 µs.
Notes:
1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause permanent damage to the device.
2. All voltages are reference to GND.
3. IDDO depends on the cycle time.
4. IDDO depends on output loading. Specified values are defined with the output open condition.
5. AC measurements are assumed tR, tF = 5 ns.
6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage
reference levels.
7. Data cannot be retained at deep power-down stand-by mode.
8. If OE# is high during the write cycle, the outputs will remain at high impedance.
9. During the output state of I/O signals, input signals of reverse polarity must not be applied.
10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
Figure 30. Read
Figure 31. Write
over 10
µs
tRCmin
CE1#
WE#
Address
tWPmin
tWCmin
CE1#
WE#
Address


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