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S71PL129JC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 14 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71PL129JC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory
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S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
Advance
Info rmation
General Description
The PL129J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write
Flash memory device organized as 8 Mwords.
The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-
grammed in-system or in standard EPROM programmers. A 12.0 V VPP is not
required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding ran-
dom access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro-
vided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
Bank
PL129J Sectors
CE# Control
1A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE1#
1B
48 Mbit (32 Kw x 96)
CE1#
2A
48 Mbit (32 Kw x 96)
CE2#
2B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE2#


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