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AD773A 데이터시트(PDF) 7 Page - Analog Devices |
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AD773A 데이터시트(HTML) 7 Page - Analog Devices |
7 / 16 page AD773A REV. 0 –7– Theory of Operation The AD773A uses a pipelined multistage architecture with a differential input, fast settling track-and-hold amplifier (THA). Traditionally, high speed ADCs have used parallel, or flash architectures. When compared to flash converters, multistage architectures reduce the power dissipation and die size by reducing the number of comparators. For example, the AD773A uses 48 comparators compared to 1023 comparators for a 10-bit flash architecture. The AD773A’s main signal path transmits differential current mode signals. Low impedance current summing techniques are employed, increasing speed by reducing sensitivity to parasitic capacitances. Pipelining allows the stages to operate concur- rently and maximizes system throughput. The input THA is followed by three 4-bit conversion stages. At any given time, the first stage operates on the most recent sample, while the second stage operates on a signal dependent on the previous sample. This process continues throughout all three stages. The twelve digital bits provided by the three 4-bit stages are combined in the correction logic to produce a 10-bit repre- sentation of the sampled analog input. Pipeline delay, or latency, is four clock cycles. New output data is provided every clock cycle and is provided in both binary and twos complement format. The AD773A will flag an out-of- range condition when the analog input exceeds the specified analog input range. Applying the AD773A DRIVING THE AD773A INPUT The AD773A may be driven in a single-ended or differential fashion. VINA is the positive input, and VINB is the negative input. In the single-ended configuration either VINA or VINB is connected to Analog Ground (AGND) while the other input is driven with a full-scale input of ±500 mV p-p. An inverted mode of operation can he achieved by simply interchanging the input connections. Both inputs of the AD773A, VINA and VINB, are high impedance and do not need to be driven by a low impedance source. Note, however, that as the source impedance increases, the input node becomes more susceptible to noise. The increased noise at the input will degrade performance. A 10 pF capacitor across VINA and VINB as shown in Figure 8 is recommended to bypass high frequency noise. V INA 26 27 10pF AD773A ±500mV V INB Figure 8. AD773A Single-Ended Input Connection INPUT CONDITIONING In some cases, it may be appropriate to buffer the input source, add dc offset, or otherwise condition the input signal of the AD773A. Choosing an appropriate op amp will vary with system requirements and the desired level of performance. Some suggested op amps are the AD9617, AD842, and AD827. Figure 9 shows a typical application where a unipolar signal is level shifted to the bipolar input range of the AD773A. Note that the reference used with the AD773A can also provide a noise-free voltage source to generate the dc offset. 2.49k Ω 499 Ω 499 Ω 2.49k Ω +2.5V ANALOG INPUT (0 TO +1V) V INA Figure 9. Unipolar to Bipolar Input Connection DIFFERENTIAL INPUT CONNECTIONS Operating the AD773A with fully differential inputs offers the advantage of rejecting common-mode signals present on both VINA and VINB. The full-scale input range of VINA and VINB when driven differentially is ±250 mV p-p as shown in Table I. Table I. AD773A’s Maximum Differential Input Voltage VINA VINB VINA–VINB +250 mV –250 mV +500 mV –250 mV +250 mV –500 mV In some applications it may be desirable to convert a single- ended signal to a differential signal before being applied to the AD773A. Figure 10 shows a single-ended to differential video line driver capable of driving doubly terminated cables. 510 Ω 75 Ω V INA 510 Ω 510 Ω 75 Ω V INB ANALOG INPUT ( ±500mV) 510 Ω 75 Ω 75 Ω Figure 10. Single-Ended to Differential Connection |
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