AD773A

REV. 0

–4–

ORDERING GUIDE

1

Temperature

Package

Model

Range

Description

Option

2

AD773AJD

0

°C to +70°C 28-Pin Ceramic DIP D-28

AD773AKD

0

°C to +70°C 28-Pin Ceramic DIP D-28

NOTES

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD773A features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS*

Parameter

With Respect to

Min

Max Units

AGND

–0.5

+6.5 V

AGND

–6.5

+0.5 V

AGND

–6.5

+6.5 V

DGND, DRGND

–0.5

+6.5 V

AGND

DGND, DRGND

–1.0

+1.0 V

–6.5

+0.5 V

CLK

–6.5

+0.5 V

REFIN

REFGND, AGND –0.5

+6.5 V

Junction Temperature

+150

°C

Storage Temperature

–65

+150

°C

Lead Temperature

(10 sec)

+300

°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum ratings for extended periods may affect device reliability.

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AD773A

TOP VIEW

(Not to Scale)

REFIN

REFGND

AGND

DGND

DRGND

AV

SS

OTR

BIT 1 (MSB)

MSB

CLK

V

INB

AGND

DRGND

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10 (LSB)

PIN DESCRIPTION

Symbol

Pin No.

Type Name and Function

AGND

5, 28

P

Analog Ground.

4

P

+5 V Analog Supply.

3, 25

P

–5 V Analog Supply.

MSB

19

DO

Inverted Most Significant Bit.

Provides twos complement out-

put data format.

OTR

20

DO

Out of Range is Active HIGH on

the leading edge of Code 0 or the

trailing edge of Code 1023. See

Output Data Format Table II.

BIT 1 (MSB)

18

DO

Most Significant Bit.

BIT 2–BIT 9

17–10

DO

Data Bit 2 through Data Bit 9.

BIT 10 (LSB) 9

DO

Least Significant Bit.

CLK

23

DI

Clock Input. The AD773A will

initiate a conversion on the falling

edge of the clock input. See the

Timing Diagram for details.

24

P

+5 V Digital Supply.

7, 22

P

+5 V Digital Supply for the out-

put drivers.

DGND

6

P

Digital Ground.

DRGND

8, 21

P

Digital Ground for the output

drivers.

REFGND

1

AI

REFGND is connected to the

ground of the external reference.

REFIN

2

AI

REFIN is the external 2.5 V ref-

erence input, taken with respect

to REFGND.

26

AI

(+) Analog input signal to the dif-

ferential input THA.

27

AI

(–) Analog input signal to the dif-

ferential input THA.

Type: AI = Analog Input; DI = Digital Input; DO = Digital

Output; P = Power.