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AM29BDD160G 데이터시트(HTML) 3 Page - Advanced Micro Devices

부품명 AM29BDD160G
상세내용  16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDD160G 데이터시트(HTML) 3 Page - Advanced Micro Devices

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DATA SHEET
1
Publication# 24960
Rev: D Amendment/+3
Issue Date: February 2, 2005
Refer to AMD’s Website (www.amd.com) for the latesst information.
Am29BDD160G
16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst
Mode, Dual Boot, Simultaneous Read/Write Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
— Data can be continuously read from one bank
while executing erase/program functions in
other bank. (–40°C to 85°C, 56 MHz and below
only)
— Zero latency between read and write opera-
tions
— Two bank architecture: 75%/25%
User-Defined x16 or x32 Data Bus
Dual Boot Block
— Top and bottom boot in the same device
Flexible sector architecture
— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8
Kbytes sectors
Manufactured
on
0.17
µm
process
technology
SecSi (Secured Silicon) Sector (256 Bytes)
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
— Factory locked and identifiable: 16 bytes for
secure, random factory Electronic Serial Num-
ber; remainder may be customer data pro-
grammed by AMD
— Customer lockable: Can be read, programmed,
or erased just like other sectors. Once locked,
data cannot be changed
Programmable Burst interface
— Interface to any high performance processor
— Modes of Burst Read Operation: Linear Burst:
4 double words (x32), 8 words (x16) and dou-
ble words (x32), and 32 words (x16) with wrap
around
Single power supply operation
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
Compatible with JEDEC standards (JC42.4)
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
High performance read access
— Initial/random access time as fast as 54 ns
— Burst access time as fast as 9 ns for ball grid
array package
Ultra low power consumption
— Burst Mode Read: 90 mA @ 66 MHz max
— Program/Erase: 50 mA max
— Standby mode: CMOS: 60 µA max
Minimum 1 million write cycles guaranteed
per sector
20 year data retention at 125°C
Versatile I/O
TM control
Device generates data output voltages and tol-
erates data input voltages as determined by
the voltage on the V
IO pin
— 1.65 V to 2.75 V compatible I/O signals
SOFTWARE FEATURES
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector
groups to prevent program or erase operations
within that sector (requires only V
CC levels)
Password Sector Protection
— A sophisticated sector protection method to
lock combinations of individual sectors and
sector groups to prevent program or erase op-
erations within that sector using a user-defin-
able 64-bit password
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
— Reduces overall programming time when issu-
ing multiple program command sequences
Data# Polling and toggle bits
— Provides a software method of detecting pro-
gram or erase operation completion
HARDWARE FEATURES
Program Suspend/Resume & Erase Sus-
pend/Resume
— Suspends program or erase operations to allow
reading, programming, or erasing in same
bank
Hardware Reset (RESET#), Ready/Busy#
(RY/BY#), and Write Protect (WP#) inputs
ACC input
— Accelerates programming time for higher
throughput during system production
Package options
— 80-pin PQFP
— 80-ball Fortified BGA


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