전자부품 데이터시트 검색엔진 |
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AD5424 데이터시트(PDF) 6 Page - Analog Devices |
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AD5424 데이터시트(HTML) 6 Page - Analog Devices |
6 / 32 page AD5429/AD5439/AD5449 Rev. 0 | Page 6 of 32 t1 t2 t3 t7 t8 t4 t5 t6 t9 t10 t11 DB15 DB0 SCLK DIN LDAC1 LDAC2 SYNC NOTES 1ASYNCHRONOUS LDAC UPDATE MODE 2SYNCHRONOUS LDAC UPDATE MODE ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram t8 t7 t12 t1 t3 t2 t4 t5 t6 DB15 (N) DB15 (N+1) DB0 (N) DB0 (N+1) DB15 (N) DB0 (N) SCLK SYNC SDIN SDO ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain and Readback Modes Timing Diagram 200 µAI OL 200 µAI OH TO OUTPUT PIN CL 50pF VOH (MIN) + VOL (MAX) 2 Figure 4. Load Circuit for SDO Timing Specifications |
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